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91400 rm (im) sk-1/22 ver.1.03 31297 preliminary overview the LC86P6560 is a cmos 8-bit single chip microcontroller with one-time prom for the lc866500 series. this microcontroller has the function and the pin description of the lc866500 series mask rom version, and 60k-byte prom. features (1) option switching by prom data the option function of the lc866500 series can be specified by the prom data. LC86P6560 can be checked the functions of the trial pieces using the mass production board. (2) internal one-time prom capacity : 61696 bytes (3) internal ram capacity : 1152 bytes used prom or ram capacity are equal rom or ram capacity of mask rom version which applies LC86P6560. mask rom version prom capacity ram capacity lc866560 61440 bytes 1152 bytes lc866556 57344 bytes 1152 bytes (4) operating supply voltage : 4.5v to 6.0v (5) instruction cycle time : 1.0 s to 366 s (6) operating temperature : -30 c to +70 c (7) the pin and the package compatible with the lc866500 series mask rom devices (8) applicable mask rom version : lc866560/lc866556 programming service we offers various services at nominal charges. these include the rom writing, the rom reading, the package stamping and the screening. contact our representative for further information. 8-bit single chip microcontrolle r with one-time programmable prom LC86P6560 ordering number : enn*6691 cmos ic
LC86P6560 2/22 notice for use LC86P6560 is provided for the first release and small shipping of the lc866500 series. at using, take notice of the followings. (1) a point of difference LC86P6560 and lc866500 series item LC86P6560 lc866560/56 operation after reset releasing the option is specified until 3ms after going to a ?h? level to the reset terminal by dgrees. the program is executed from 00h of the program counter. the program is executed from 00h of the program counter immediately after going to a ?h? level to reset terminal. pull-down resistor of the following pins s0/t0 ? s6/t6 s7/t7 ? s15/t15 s16 ? s31 s32 ? s47 s48 ? s51 pull-down resistor provided/not provided not provided provided (fixed) provided (fixed) not provided not provided pull-down resistor provided/not provided specified by the option provided (fixed) specified by the option specified by the option not provided power dissipation refer to ?electrical characteristics? on the semiconductor news. LC86P6560 uses 256 bytes that is addressed on ff00h to ffffh in the program memory as the option configuration data area. this option configuration cannot execute all options which lc866500 series have. next tables show the options that correspond and not correspond to LC86P6560. a kind of the option corresponding of the LC86P6560 a kind of option pins, circuits contents of the option 1. n-channel open drain output 2. cmos output *1 port 0 1. pull-up mos tr. proveded 2. pull-up mos tr. not provided *2 port 1 *1 1. input : programmable pull-up mos tr. output : n-channel open drain 2. input : programmable pull-up mos tr. output : cmos input/output form of input/output ports port 3 *2 1. input : no programmable pull-up mos tr. output : n-channel open drain 2. input : programmable pull-up mos tr. output : cmos *1) specified in a bit *2) specified in nibble unit. the port of n-channel open drain output does not have the pull-up mos tr.. a kind of the option not corresponding of the LC86P6560 a kind of option pins, circuits LC86P6560 lc866560/56 pull-down resistor of the high voltage withstand output terminals s0/t0 to s6/t6 s16 to s31 s32 to s47 not provided provided (fixed) not provided specified by the option specified by the option specified by the option
LC86P6560 3/22 (1) option the option data is created by the option specified program ?su86k.exe?. the created option data is linked to the program area by linkage loader ?l86k.exe?. (2) rom space lc86e7248 and lc867200 series use 256 bytes that is addressed on 0ff00h to 0ffffh in the program memory as the option specified data area. these program memory capacity are 49152 bytes that is addressed on 0000h to 0bfffh. (3) ordering information 1. when ordering the identical mask rom and prom devices simultaneously. provide an eprom containing the target memory contents together with the separate order forms for each of the mask rom and prom versions. 2. when ordering a prom device. provide an eprom containing the target memory contents together with an order form. 0ffffh 0ff00h 0efffh 0dfffh 0cfffh 0bfffh 0afffh 9fffh 8fffh 7fffh 6fffh 5fffh 4fffh 3fffh 2fffh 1fffh 0fffh 0000h option data area 256 bytes program area 48k bytes option data area program area 40k bytes lc867248 lc867240 option data area program area 32k bytes lc867232 option data area lc867224 program area 28k bytes
LC86P6560 4/22 how to use (1) specification of option programming data for prom of the LC86P6560 is required. debugged evaluation file (eva file) must be converted to an intel-hex formatted file (hex file) with file converter program, eva2hex.exe. the hex file is used as the programming data for the lc86p6548. (2) how to program for the prom LC86P6560 can be programmed by the prom programmer with attachment ; w86ep6548q. recommended prom programmer productor eprom programmer advantest r4945, r4944, r4943 andou af-9704 aval pkw-1100, pkw-3000 minato electronics model 1890a ?27512 (vpp=12.5v) intel high speed programming? mode available. the address must be set to ?0 to 0ffffh? and a jumper (dasec) must be set to ?off? at programming. (3) how to use the data security function ?data security? is the disabled function to read the data of the prom. the following is the process in order to execute the data security. 1. set ?on? the jumper of attachment. 2. program again. then prom programmer displays the error. the error means normally activity of the data security. it is not a trouble of the prom programmer or the lsi. notes data security is not executed when the data of all address have ?ffh? at the sequence 2 above. the programming by a sequential operation ?blank ? program ? verify? cannot be executed data security at the sequence 2 above. set to ?off? the jumper after executing the data security. w86ep6548q data security not data security 1 pin mark of lsi 1 pin
LC86P6560 5/22 pin assignment package dimension (unit : mm) 3151 sanyo : qip-100e 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 s48/pg0 s49/pg1 s50/pg2 s51/pg3 p00 p01 p02 p03 vss2 vdd2 p04 p05 p06 p07 p10/so0 p11/si0/sb0 p12/sck0 p13/so1 p14/si1/sb1 p15/sck1 s19/pc3 s18/pc2 s17/pc1 s16/pc0 vdd3 s15/t15 s14/t14 s13/t13 s12/t12 s11/t11 s10/t10 s9/t9 s8/t8 s7/t7 s6/t6 s5/t5 s4/t4 s3/t3 s2/t2 s1/t1 s47/pf7 s46/pf6 s45/pf5 s44/pf4 s43/pf3 s42/pf2 s41/pf1 s40/pf0 vdd4 s39/pe7 s38/pe6 s37/pe5 s36/pe4 s35/pe3 s34/pe2 s33/pe1 s32/pe0 s31/pd7 s30/pd6 s29/pd5 s28/pd4 s27/pd3 s26/pd2 s25/pd1 s24/pd0 s23/pc7 s22/pc6 s21/pc5 s20/pc4 vp p16/buz z p17/pwm0 p30 p31 p32 p33 p34 p35 p36 p37 p70/int0 res xt1/p74 xt2/p75 vss1 cf1 cf2 vdd1 p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 p86/an6 p87/an7 p71/int1 p72/int2/t0i n p72/int3/t0i n s0/t0
LC86P6560 6/22 system block diagram interrupt control a15-a0 d7-d0 ta ce oe dasec standby control clock generator cf rc x?tal base timer sio0 sio1 timer 0 timer 1 adc int0-3 noise filter sio automatic transmission ram (128 bytes) vfd controller high voltage output bus interface port 1 port 3 port 7 port 8 ir pla prom control prom(48kb) pc acc b register c register alu psw rar ram stack pointer port 0 watch dog timer
LC86P6560 7/22 LC86P6560 pin description pin name i/o function description option prom mode vss1,2 - power pin (-) *4 - - vdd1,2,3,4 - power pin (+) *4 - - vp - power pin (+) for the vfd output pull-down resist - - port0 p00 ? p07 i/o 8-bit input/output port input/output in nibble units input for port 0 interrupt input for hold release 15v withstand at n-channel open drain output pull-up resistor : provided/not provided (each nibble) output form : cmos/n-channel open drain (each bit) - port1 p10 ? p17 i/o 8-bit input/output port input/output can be specified in bit unit other pin functions p10 sio0 data output p11 sio0 data input/bus input/output p12 sio0 clock input/output p13 sio1 data output p14 sio1 data input/bus input/output p15 sio1 clock input/output p16 buzzer output p17 timer 1 output (pwm0 output) output form : cmos/n-channel open drain (each bit) data line d0 to d7 port3 p30 ? p37 i/o 8-bit input/output port input/output in bit unit 15v withstand at n-channel open drain output output form : cmos/n-channel open drain (each bit) - 4-bit input/output port input/output in bit unit 2-bit input port other pin functions p70 : int0 input/hold release/n-channel tr. output for watchdog timer p71 : int1 input/hold release input p72 : int2 input/timer 0 event input p73 : int3 input with noise filter/timer 0 event input p74 : 32.768khz crystal oscillation terminal xt1 p75 : 32.768khz crystal oscillation terminal xt2 interrupt received form, vector address - rising falling rising & falling high level low level vector int0 enable enable disable enable enable 03h int1 enable enable disable enable enable 0bh int2 enable enable enable disable disable 13h port7 p70-p73 p74 -p75 i/o i int3 enable enable enable disable disable 1bh prom control signals dasec (*1) oe (*2) ?be (*3) ce
LC86P6560 8/22 pin name i/o function description option prom mode port8 p80-p83 p84-p87 i i/o 4-bit input/output port input/output in bit unit 4-bit input port other function ad input port (8 port pins) - - s0/t0 to s6/t6 *6 o output for vfd display controller segment/timing in common - - s7/t7 to s15/t15 *7 o output for vfd display controller segment/timing with internal pull-down resistor in common internal pull-down resistor output - ta (*5) s16 to s31 *8 i/o output for vfd display controller segment other function s16 : high voltage input port pc0 s17 : high voltage input port pc1 s18 : high voltage input port pc2 s19 : high voltage input port pc3 s20 : high voltage input port pc4 s21 : high voltage input port pc5 s22 : high voltage input port pc6 s23 : high voltage input port pc7 s24 : high voltage input port pd0 s25 : high voltage input port pd1 s26 : high voltage input port pd2 s27 : high voltage input port pd3 s28 : high voltage input port pd4 s29 : high voltage input port pd5 s30 : high voltage input port pd6 s31 : high voltage input port pd7 - address input a15 to a0 s32 to s47 *9 i/o output for vfd display controller segment other function s32 : high voltage input port pe0 s33 : high voltage input port pe1 s34 : high voltage input port pe2 s35 : high voltage input port pe3 s36 : high voltage input port pe4 s37 : high voltage input port pe5 s38 : high voltage input port pe6 s39 : high voltage input port pe7 s40 : high voltage i/o port pf0 s41 : high voltage i/o port pf1 s42 : high voltage i/o port pf2 s43 : high voltage i/o port pf3 s44 : high voltage i/o port pf4 s45 : high voltage i/o port pf5 s46 : high voltage i/o port pf6 s47 : high voltage i/o port pf7 - -
LC86P6560 9/22 pin name i/o function description option prom mode s48 to s51 *9 i/o output for vfd display controller segment other function s48 : high voltage i/o port pg0 s49 : high voltage i/o port pg1 s50 : high voltage i/o port pg2 s51 : high voltage i/o port pg3 - - res i reset pin - - xt1/ p74 i input pin for 32.768khz crystal oscillation other function xt1 : input port p74 in case of non use, connect to vdd1. - - xt2/p75 o output pin for 32.768khz crystal oscillation other function xt2 : input port p75 in case of non use, connect to vdd1 at using as port or unconnect at using as oscillation. - - cf1 i input pin for ceramic resonator oscillation - - cf2 o output pin for ceramic resonator oscillation - - *all of port options (except pull-up resistor of port 0) can be specified in bit unit. *1 memory select input for data security *2 output enable input *3 chip enable input *4 connect like the following figure to reduce noise into a vdd1 terminal. shorted the vss1 terminal to the vss2 terminal and to make the back-up time long. *5 ta ! prom control signal input *6 s0/t0 to s6/t6 : not provided the pull-down resistor *7 s7/t7 to s15/t15 : provided the pull-down resistor (fixed) *8 s16 to s31 : provided the pull-down resistor (fixed) *9 s32 to s51 : not provided the pull-down resistor power supply lsi vdd1 back-up capacitor vdd2 vdd3 vss2 vss1 vdd4 vfd powers
LC86P6560 10/22 1. absolute maximum ratings at vss1=vss2=0v and ta=25 c ratings parameter symbol pins conditions v dd [v] min. typ. max. unit supply voltage vddmax vdd1, vdd2 vdd3, vdd4 vdd1=vdd2= vdd3=vdd4 -0.3 +7.0 vi(1) ports 74 ,75 ports 80,81,82,83 port 8 res -0.3 vdd+0.3 input voltage vi(2) vp vdd-45 vdd+0.3 output voltage vo s0/t0 to s15/t15 vdd-45 vdd+0.3 vio(1) port 1 ports 70,71,72,73 ports 84,85,86,87 ports 0, 3 at cmos output option -0.3 vdd+0.3 vio(2) ports 0, 3 at n-ch open drain output option -0.3 15 input/output voltage vio(3) s16 to s51 vdd-45 vdd+0.3 v ioph(1) ports 0, 1, 3 cmos output at each pins -10 ioph(2) s0/t0 to s15/t15 at each pins -30 peak output current ioph(3) s16 to s51 at each pins -15 ioah(1) port 0 the total of all pins -30 ioah(2) ports 1, 3 the total of all pins -30 ioah(3) s0/t0 to s15/t15 the total of all pins -55 ioah(4) s16 to s27 the total of all pins -60 ioah(5) s28 to s39 the total of all pins -60 high level output current total output current ioah(6) s40 to s51 the total of all pins -60 iopl(1) ports 0, 1, 3 at each pins 20 peak output current iopl(2) ports 70,71,72,73 ports 84,85,86,87 at each pins 15 ioal(1) port 0 the total of all pins 60 ioal(2) ports 1, 3, 70 the total of all pins 50 low level output current total output current ioal(3) ports 71,72,73 ports 84,85,86,87 the total of all pins 20 ma maximum power dissipation pdmax qfp100e ta=-30 to+70 c 500 mw operating temperature range topr -30 +70 storage temperature range tstg -55 +125 c
LC86P6560 11/22 2. recommended operating range at ta=-30 c to +70 c, vss1=vss2=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit operating supply voltage range vdd vdd1=vdd2= vdd3=vdd4 0.98 s t cyc 400 s 4.5 6.0 hold voltage vhd vdd1=vdd2 rams and the registers hold voltage at hold mode. 2.0 6.0 pull-down voltage vp vp 4.5-6.0 -35 vdd vih(1) port 0 cmos output option output disable 4.5-6.0 0.33vdd +1.0 vdd vih(2) port 0 at n-ch open drain output output disable 4.5-6.0 0.75vdd 13.5 vih(3) port 1 ports 72,73 port 3 at cmos output option output disable 4.5-6.0 0.75vdd vdd vih(4) port 3 at n-ch open drain output output disable tr. off 4.5-6.0 0.75vdd 13.5 vih(5) port 70 port input/interrupt port 71 res output disable 4.5-6.0 0.75vdd vdd vih(6) port 70 watchdog timer output disable 4.5-6.0 0.9vdd vdd vih(7) port 8 ports 74 ,75 output disable 4.5-6.0 0.75vdd vdd input high voltage vih(8) s16 to s51 output p-channel tr. off 4.5-6.0 0.33vdd +1.0 vdd vil(1) port 0 at cmos output option output disable 4.5-6.0 vss 0.2vdd vil(2) port 0 at n-ch open drain output output disable 4.5-6.0 vss 0.25vdd vil(3) ports 1,3 ports 72,73 output disable 4.5-6.0 vss 0.25vdd vil(4) port 70 port input/interrupt port 71 res output disable 4.5-6.0 vss 0.25vdd vil(5) port 70 watchdog timer output disable 4.5-6.0 vss 0.8vdd -1.0 vil(6) port 8 ports 74 ,75 output disable 4.5-6.0 vss 0.25vdd input low voltage vil(7) s16 to s51 output p-channel tr. off 4.5-6.0 vp 0.2vdd v operation cycle time t cyc 4.5-6.0 0.98 400 s continue.
LC86P6560 12/22 ratings parameter symbol pins conditions vdd[v] min. typ. max. unit fmcf(1) cf1, cf2 6mhz (ceramic resonator oscillation) refer to figure 1 4.5-6.0 6 fmcf(2) cf1, cf2 3mhz (ceramic resonator oscillation) refer to figure 1 4.5-6.0 3 fmrc rc oscillation 4.5-6.0 0.3 0.8 3.0 mhz oscillation frequency range (note 1) fsxtal xt1, xt2 32.768khz (crystal oscillation) refer to figure 2 4.5-6.0 32.768 khz tmscf(1) cf1, cf2 6mhz (ceramic resonator oscillation) refer to figure 3 4.5-6.0 tmscf(2) cf1, cf2 3mhz (ceramic resonator oscillation) refer to figure 3 4.5-6.0 ms oscillation stabilizing time period (note 1) tssxtal xt1, xt2 32.768khz (crystal oscillation) refer to figure 3 4.5-6.0 s (note 1) the oscillation constant is shown on table 1.
LC86P6560 13/22 3. electrical characteristics at ta=-30 c to +70 c, vss1=vss2=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit iih(1) ports 0,3 of open drain output output disable vin=13.5v (including the off- leak current of the output tr.) 4.5-6.0 5 iih(2) port 0 without pull-up mos tr. ports 1,3 output disable pull-up mos tr. off. vin=vdd (including the off- leak current of the output tr.) 4.5-6.0 1 iih(3) ports 70,71,72,73 port 8 output disable vin=vdd (including the off- leak current of the output tr.) 4.5-6.0 1 iih(4) res vin=vdd 4.5-6.0 1 iih(5) ports 74 ,75 vin=vdd 4.5-6.0 1 input high current iih(6) s32 to s51 without pull-down resistor output p-channel tr. off vin=vdd 4.5-6.0 1 iil(1) ports 1,3 vport 0 without pull-up mos tr. output disable pull-up mos tr. off. vin=vss (including the off- leak current of the output tr.) 4.5-6.0 -1 iil(2) ports 70,71,72,73 port 8 output disable vin=vss (including the off- leak current of the output tr.) 4.5-6.0 -1 iil(3) res vin=vss 4.5-6.0 -1 input low current iil(4) ports 74 ,75 vin=vss 4.5-6.0 -1 a voh(1) ioh=-1.0ma 4.5-6.0 vdd-1 voh(2) ports 0,1,3 of cmos output ioh=-0.1ma 4.5-6.0 vdd-0.5 voh(3) ioh=-20ma 4.5-6.0 vdd-1.8 voh(4) s0/t0 to s15/t15 ioh=-1ma the current of any unmeasurement pin is not over 1ma. 4.5-6.0 vdd-1 voh(5) ioh=-5ma 4.5-6.0 vdd-1.8 output high voltage voh(6) s16 to s51 the current of any unmeasurement pin is not over 1ma. 4.5-6.0 vdd-1 vol(1) iol=10ma 4.5-6.0 1.5 vol(2) ports 0, 1, 3 iol=1.6ma 4.5-6.0 0.4 vol(3) port 70 iol=1ma 4.5-6.0 0.4 output low voltage vol(4) ports 71,72,73 ports 84,85,86,87 iol=1.6ma 4.5-6.0 0.4 v pull-up mos tr. resistor rpu ports 0, 1, 3 voh=0.9vdd 4.5-6.0 15 40 70 k ? continue.
LC86P6560 14/22 ratings parameter symbol pins conditions vdd[v] min. typ. max. unit ioff(1) output p-ch tr. off vout=vss 4.5-6.0 -1 output off- leak current ioff(2) s0/t0 to s6/t6, s32 to s51 without pull-down resistor output p-ch tr. off vout=vdd-40v 4.5-6.0 -30 a resistance of the low level hold tr. rinpd s16 to s51 output p-ch tr. off using as input ports 4.5-6.0 200 high voltage pull-down resistor rpd s7/t7 to s15/t15, s16 to s31 output p-ch tr. off vout=3v vp=-30v 5.0 60 100 200 vp pull-down resistor rvppd vp vss=gnd vp=-30v 5.0 60 100 200 k ? hysteresis voltage vhis port 1 ports 70,71,72,73,75 res output disable 4.5-6.0 0.1vdd v pin capacitance cp all pins f=1mhz unmeasurement terminals for the input are set to vss level. ta=25 c 4.5-6.0 10 pf 4. serial input/output characteristics at ta=-30 c to +70 c, vss1=vss2=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit cycle t ckcy (1) 2 low level pulse width t ckl (1) 1 input clock high level pulse width t ckh (1) sck0, sck1 refer to figure 5. 4.5-6.0 1 cycle t ckcy (2) 2 low level pulse width t ckl (2) 1/2 t ckcy serial clock output clock high level pulse width t ckh (2) sck0, sck1 use pull-up resistor (1k ? ) when opendrain output. refer to figure 5. 4.5-6.0 1/2 t ckcy t cyc data set up time t ick 0.1 serial input data hold time t cki si0,si1 sb0,sb1 data set-up to sck0,1 data hold from sck0,1 refer to figure 5. 4.5-6.0 0.1 output delay time (serial clock is external clock) t cko(1) 7/12 t cyc +0.2 serial output output delay time (serial clock is internal clock) t cko(2) so0,so1 sb0,sb1 use pull-up resistor (1k ? ) when open drain output. data hold from sck0,1 refer to figure 5. 4.5-6.0 1/3 t cyc +0.2 s
LC86P6560 15/22 5. pulse input conditions at ta=-30 c to +70 c, vss1=vss2=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit tpih(1) tpil(1) int0, int1 int2/t0in interrupt acceptable timer0-countable 4.5-6.0 1 tpih(2) tpil(2) int3/t0in (the noise rejection clock is selected to 1/1.) interrupt acceptable timer0-countable 4.5-6.0 2 tpih(3) tpil(3) int3/t0in (the noise rejection clock is selected to 1/16.) interrupt acceptable timer0-countable 4.5-6.0 32 tpih(4) tpil(4) int3/t0in (the noise rejection clock is selected to 1/64.) interrupt acceptable timer0-countable 4.5-6.0 128 t cyc high/low level pulse width tpil(5) res reset acceptable 4.5-6.0 200 s 6. ad converter characteristics at ta=-30 c to + 70 c, vss1=vss2=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit resolution n 4.5-6.0 8 bit absolute precision (note 2) et 4.5-6.0 1.5 lsb ad conversion time = 16 tcyc (adcr2=0) (note 3) 15.68 (tcyc= 0.98 s) 65.28 (tcyc= 4.08 s) conversion time tcad ad conversion time = 32 tcyc (adcr2=1) (note 3) 4.5-6.0 31.36 (tcyc= 0.98 s) 130.56 (tcyc= 4.08 s) s analog input voltage range vain 4.5-6.0 vss vdd v iainh vain=vdd 4.5-6.0 1 analog port input current iainl an0 to an7 vain=vss 4.5-6.0 -1 a (note 2) absolute precision excepts quantizing error (1/2 lsb). (note 3) the conversion time means the time from executing the ad conversion instruction to setting the complete digital conversion value to the register.
LC86P6560 16/22 7. current dissipation characteristics at ta=-30 c to +70 c, vss1=vss2=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit iddop(1) fmcf=6mhz ceramic resonator oscillation internal rc oscillation stops fsxtal=32.768khz crystal oscillation system clock : cf oscillation 1/1 divided 4.5-6.0 14 33 iddop(2) fmcf=3mhz ceramic resonator oscillation internal rc oscillation stops fsxtal=32.768khz crystal oscillation system clock : cf oscillation 1/2 divided 4.5-6.0 6 18 iddop(3) fmcf=0hz (when oscillation stops) fsxtal=32.768khz crystal oscillation system clock : rc oscillation 1/2 divided 4.5-6.0 4 13 ma current dissipation during basic operation (note 4) iddop(4) fmcf=0hz (when oscillation stops) fsxtal=32.768khz crystal oscillation system clock : crystal oscillation internal rc oscillation stops 1/2 divided 4.5-6.0 3 10 a continue.
LC86P6560 17/22 ratings parameter symbol pins conditions vdd[v] min. typ. max. unit iddhalt(1) halt mode fmcf=6mhz ceramic resonator oscillation internal rc oscillation stops fsxtal=32.768khz crystal oscillation system clock : cf oscillation 1/1 divided 4.5-6.0 5 14 iddhalt(2) halt mode fmcf=3mhz ceramic resonator oscillation internal rc oscillation stops fsxtal=32.768khz crystal oscillation system clock : cf oscillation 1/2 divided 4.5-6.0 2.2 7 ma iddhalt(3) halt mode fmcf=0hz (when oscillation stops) fsxtal=32.768khz crystal oscillation system clock : rc oscillation 1/2 divided 4.5-6.0 400 1600 current dissipation in halt mode (note 4) iddhalt(4) halt mode fmcf=0hz (when oscillation stops) fsxtal=32.768khz crystal oscillation system clock : crystal oscillation internal rc oscillation stops 1/2 divided 4.5-6.0 25 100 current dissipation in hold mode (note 4) iddhold hold mode 4.5-6.0 0.05 30 a (note 4) the currents of the output transistors and the pull-up mos transistors are ignored.
LC86P6560 18/22 table 1. ceramic resonator oscillation guaranteed constant (main clock) oscillation type maker oscillator c1 c2 csa6.00mg murata cst6.00mgw kbr-6.0msb pbrc6.00a (chip type) kbr-6.0mkc 6mhz ceramic resonator oscillation kyocera pbrc6.00b (chip type) csa3.00mg murata cst3.00mgw 3mhz ceramic resonator oscillation kyocera kbr-3.0ms * both c1 and c2 must use k rank (10%) and sl characteristics. table 2. crystal oscillation recommended constant (sub clock) oscillation type maker oscillator c3 c4 rf rd 32.768khz crystal oscillation * both c3 and c4 must use j rank (5%) and ch characteristics. (it is about the application, which is not in need of high precision. use k rank (10%) and sl characteristics.) (notes) since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length. if you use other oscillators herein, we provide no guarantee for the characteristics. figure 1 ceramic oscillation circuit figure 2 crystal oscillation circuit to be determind c1 c2 cf cf2 cf1 c3 rd c4 x?tal xt2 xt1 rf
LC86P6560 19/22 figure 3 oscillation stable time operation mode xt1, xt2 cf1, cf2 internal rc resonator oscillation res instruction execution mode instruction execution mode instruction execution mode ocr6=1 reset valid unfixed tssxtal tmscf reset time vdd vdd limit 0v power supply operation mode xt1, xt2 cf1, cf2 hold release signal hold tssxtal tmscf internal rc resonator oscillation
LC86P6560 20/22 figure 4 reset circuit figure 5 serial input / output test condition figure 6 pulse input timing condition (note) fix the value of c res , r res that is sure to reset until 200 s, after power supply has been over inferior limit of supply voltage. so0, so1 sb0, sb1 si0 si1 sck0 sck1 50pf 1k ? vdd tcko tcki tick tckh tckl tckcy 0.5vdd tpih tpil c res vdd r res res
LC86P6560 21/22 notice for use ? the construction of the one-time programmable microcomputer with a blank built-in prom makes it impossible for sanyo to completely factory-test it before shipping. to probe reliability of the programmed devices, the screening procedure shown in the following figure should always be followed. ? it is not possible to perform a writing test on the blank prom. 100% yield, therefore, cannot be guaranteed. ? keeping the dry packing the environment must be held at a temperature of 30 c or less and a humidity level of 70% or less. ? after opening the packing the preparation procedures shown in the following figure should always be followed prior to mounting the packages on the substrate. after opening the packing, a controlled environment must be maintained until soldering. the environment must be held at a temperature of 30 c or less and a humidity level of 70% or less. please solder within 96 hours. unused devices should be kept in the dry atmosphere such as inside of desiccator or dry these up before assembling on the board. a. shipping with a blank prom b. shipping with a programmed prom (programming the data by yourself) (programming the data by sanyo) qfp qfp writing data for program/verifying recommended process of screening heat-soak 1505 c,24 hr +1 -0 reading ascertain of program vdd=50.5v mounting mounting
LC86P6560 22/22 memo: ps

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